Stock Code

874608

MICROTEST

Dedicated to becoming a world-leading provider of AI computing power testing equipment and solutions

All

All
Product Management
News
Corporate Video
Corporate Brochure

Home page

Service Hotline

0755-33691022

Email:

Microtest@microtesttech.com

Fax:

0755-33699513

Address:

Floor 1, No. 2, Dongtang Industrial Zone, Innovation Road, Shatou Community, Shajing Street, Baoan District, Shenzhen

Microtest applied for a patent for JTAG delay self-calibration processing used in boundary scan testing, improving signal test speed and signal stability.

Release Date: 2025-04-29 00:00

On April 29, 2025, Microtest applied for a patent named “A JTAG delay self-calibration processing method and system for boundary scan test”, with publication number CN119881616A and application date in January 2025.

2025 Year 4 Month 29 Day news, Microtest Stock applied for a patent named " A JTAG delay self-correction processing method and system ” patent publication number CN119881616A , application date 2025 Year 1 Month.

Patent abstract: This invention discloses a JTAG delay self-correction processing method and system for boundary scan testing, which generates and obtains the first data corresponding to the boundary scan testing system to be JTAG delay correction processing; wherein, the first data is JTAG signal data, including clock signal data, status signal data, input signal data and return signal data; based on the first data, the second data corresponding to the boundary scan testing system is generated; wherein, the second data is the delay data in the boundary scan testing system; based on the second data, the data delay state in the boundary scan testing system is corrected in real time, and the self-correction function can be realized, that is, when the user uses the product, there is no need to obtain the delay, only through the host computer one-click BS chain delay correction, which improves the signal test rate and signal stability, and significantly improves the convenience of delay correction and reduces the difficulty of system delay correction operation.